Conference paper

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS

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A 16 Gb/s receiver implemented in 22 nm SOI CMOS technology is reported. The analog frontend accepts a rail-to-rail input common-mode imposed from the transmitter side. It consists of a baseline wander compensated passive linear equalizer that AC-couples the received signal to the subsequent active CTLE with a regulated common-mode level. The programmable passive linear equalizer features a frequency response suitable for low-frequency equalization such as for skin-effect losses. When its zero is programmed at 200 MHz minimum frequency, the measured maximum mid-band peaking is 7 dB. The receiver architecture is half-rate and comprises an 8-tap DFE and a baud-rate CDR. With no FFE at the transmitter, 0.9 Vppd PRBS31 NRZ data are recovered error-free (BER<10-12) across a copper channel with 34 dB attenuation at 8 GHz.