Publication
VLSI Circuits 2018
Conference paper

A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS

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Abstract

We present a digital implementation of a TX precoder/equalizer that, similar to a Tomlinson-Harashima Precoder (THP), provides a decision feedback equalizer (DFE) function on the transmitter side. The TX-DFE avoids error propagation together with the complexity and power overhead of an RX-DFE. The I-tap precoder is implemented using a table-based digital FFE, which also shapes the channel pulse to a 1 +0.5D response and cancels pre-cursor inter-symbol interference (lSI). The combined precoder/8-tap FFE was implemented in 14nm FinFet CMOS, and was measured to operate at 112Gb/s consuming 0.3pJ/bit energy.

Date

22 Oct 2018

Publication

VLSI Circuits 2018

Authors

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