IEDM 1997
Conference paper

0.25 μm CMOS SOI technology and its application to 4 Mb SRAM


In this paper a 0.25 μm SOI CMOS technology is described. It uses undepleted SOI devices with nominal channel length of 0.15 μm, minimum channel length in the 0.1 μm range, supply voltage of 1.8 V, local interconnect, 6 levels of metal, and same ground rules as the comparable bulk 0.25 μm CMOS. Key technology elements considered include device, performance, reliability, ESD, and circuit functionality. Using this SOI CMOS, a 4 Mb SRAM is demonstrated. This is the highest performance 0.25 μm CMOS technology reported to date.