Krishnan Kailas


Krishnan Kailas




Senior Research Scientist


IBM Research - Yorktown Heights Yorktown Heights, NY USA


Krishnan Kailas is a Senior Research Scientist at IBM Thomas J. Watson Research Center, Yorktown Heights, New York. He joined IBM Research in 2001 and has since led and contributed to several exploratory systems research projects to develop and bring emerging technologies into IBM products. He is currently working on code translation and summarization systems using large-language models in the AI for Code research group. Prior to this, he led an exploratory project to define the architecture and compiler for analog AI accelerators for training deep neural networks at the IBM Research AI Hardware Center.

Dr. Kailas has contributed to the design and development of a wide spectrum of systems and research topics such as embedded real-time systems, hard real-time operating systems, VLSI design, temporal accuracy of microprocessors, high-speed network traffic shapers, VLIW architectures, binary translation systems, static (compiler) and dynamic (instruction scheduling unit) scheduling and resource allocation algorithms, computer architecture and microarchitecture, compilers and code generators, statically scheduled low-power DSP architecture exploiting fully-exposed pipelines, formal verification, performance modelling and analysis, full-system emulators and tools for IBM z mainframe processor design, computer architectures exploiting 3D integration, qubit control for quantum computing, and AI compute accelerators exploiting approximate digital and analog in-memory computing techniques.  Many of his research contributions have been incorporated into IBM microprocessors and systems. Dr. Kailas is a recipient of several IBM Research division technical achievement awards, and the 2021 Mahboob Khan Outstanding Liaison award from the Semiconductor Research Corporation.

He received a Ph.D. from the University of Maryland, College Park, where his dissertation research focused on the microarchitecture and code generation issues of clustered ILP processors. Prior to graduate studies at Maryland, he worked at Bhabha Atomic Research Center designing real-time operating systems, application and system software, and hardware for embedded systems for real-time process control and instrumentation.

Dr. Kailas served as the IBM Research division's Campus Relationship Manager for University of Maryland College Park during 2005-2019.  He has been a member of the technical advisory board (TAB) of GRC programs at Semiconductor Research Corporation (SRC) since 2016.  He served as the vice-chair of the TAB for the SRC System-level Design (SLD) program (2018-2019), and the inaugural chair of the TAB for the AI Hardware research (AIHW) program (2019-2021).  In addition, he has been an organizer for the IBM IEEE AI Compute Symposium.

Here're some of the research projects he has contributed to:

  • eLite: ultra-low power DSP
  • DAISY: dynamic binary translation
  • Maruti: hard real-time OS

Selected Publications:

  • Shu-Ting Wang, Hanyang Xu, Amin Mamandipoor, Rohan Mahapatra, Byung Hoon Ahn, Soroush Ghodrati, Krishnan Kailas, Mohammad Alian, Hadi Esmaeilzadeh, Data Motion Acceleration: Chaining Cross-Domain Multi Accelerators, 30th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2024), p.1043-1062, March, 2024.
  • Philip G. Emma, Alper Buyuktosunoglu, Michael B. Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime H. Moreno, 3D stacking of high-performance processors, 20th IEEE International Symposium on High Performance Computer Architecture (HPCA 2014), p.500-511, February, 2014.
  • Krishnan Kailas, Viresh Paruthi, Brian Monwai, Formal Verification of Correctness and Performance of Random Priority-based Arbiters, 9th International Conference on Formal Methods in Computer-Aided Design (FMCAD 2009), p.101-107, November, 2009.
  • Ashwin Swaminathan, Yinian Mao, Min Wu, Krishnan Kailas, Data Hiding in Compiled Program Binaries for Enhancing Computer System Performance, 7th International Workshop on Information Hiding (IH 2005), Lecture Notes in Computer Science Vol. 3727, Springer, p.357-371, June 2005.
  • J.H. Moreno, V. Zyuban, U. Shvadron, F. Neeser, J. Derby, M. Ware, K. Kailas, A. Zaks, A. Geva, S. Ben-David, S. Asaad, T. Fox, M. Biberstein, D. Naishlos, H. Hunter, An innovative low-power high-performance programmable signal processor for digital communications, IBM Journal of Research and Development, Vol. 47, No. 2/3, p. 299-326, March/May, 2003.
  • Krishnan Kailas, Manoj Franklin, Kemal Ebcioglu, A Register File Architecture and Compilation Scheme for Clustered ILP Processors, 8th International Euro-Par Conference (Euro-Par 2002), Lectures Notes in Computer Science, Vol. 2400, Springer-Verlag, p.500-511, August, 2002.
  • Krishnan Kailas, Kemal Ebcioglu, Ashok Agrawala, CARS: A New Code Generation Framework for Clustered ILP Processors, Proc. of the 7th International Symposium on High Performance Computer Architecture (HPCA-7), p.133-143, January, 2001.
  • Kemal Ebcioglu, Jason Fritts, Stephen Kosonocky, Michael Gschwind, Erik Altman, Krishnan Kailas, Terry Bright, An Eight Issue Tree-VLIW Processor for Dynamic Binary Translation, Proc. of International Conference on Computer Design ICCD'98, p.488-495, October 1998.

See Google Scholar for a complete list.

Selected Patents:

  • System Design Using Accurate Performance Models, 6/30/2020, Issued as US Patent 10,699,049 (Krishnan Kailas).
  • 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, 9/13/2016, Issued as US Patent 9,442,884 and 9,471,535 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas).
  • Memory Architectures Having Wiring Structures that Enable Different Access Patterns in Multiple Dimensions, 11/17/2015, Issued as US Patent 9,190,118 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas).
  • Enhanced Case-splitting based Property Checking, 03/10/2015, Issued as US Patent 8,978,001 and 8,997,030 (Krishnan Kailas, Hari Mony).
  • 3-D Stacked Multiprocessor Structures and Methods To Enable Reliable Operation Of Processors At Speeds Above Specified Limits, 08/05/2014 Issued as US Patent 8,799,710 and 8,826,073 (A. Buyuktosunoglu, P. Emma, M. B. Healy, A. Hartstein, Krishnan Kailas).
  • Method and Structure for Provably Fair Random Number Generator, 11/13/2012, Issued as US Patent 8,312,071 and 9,063,807 (Krishnan Kailas, Brian Monwai, Viresh Paruthi).
  • Method and Apparatus for Fast Synchronization and Out-of-order Execution of Instructions in a Meta-program based Computing System, 10/30/2012, Issued as US Patent 8,301,870 (Krishnan Kailas).
  • Method and Apparatus for Application-specific Dynamic Cache Placement, 11/16/2010, Issued as US Patent 7,836,256 (Krishnan Kailas, Rajiv Ravindran, Zehra Sura).
  • Bounded Starvation Checking of an Arbiter Using Formal Verification, 07/06/2010, Issued as US Patent 7,752,369 (Krishnan Kailas, Brian Monwai, Viresh Paruthi).
  • Method and System for Tracking Instruction Dependency in an Out-of-Order Processor, 05/04/2010, Issued as US Patent 7,711,929 (Bill Burky, Krishnan Kailas).
  • Method and Apparatus for a Computing System Using Meta Program Representation, 02/16/2010, Issued as US Patent 7,665,070 (Krishnan Kailas).
  • Method and system for dependency tracking and flush recovery for an out-of-order microprocessor, 02/09/2010, Issued as US Patent 7,660,971 (Vikas Agarwal, Bill Burky, Krishnan Kailas, Balaram Sinharoy).
  • Method and apparatus for register renaming using multiple physical register files and avoiding associative search, 03/17/2009, Issued as US Patent 7,506,139 (Bill Burky, Krishnan Kailas, Balaram Sinharoy).
  • Method and apparatus for dynamic priority-based cache replacement, 03/10/2009, Issued as US Patent 7,502,890 (Krishnan Kailas, Rajiv Ravindran, Zehra Sura).
  • Computer processing system employing an instruction schedule cache, 01/02/2009, Issued as US Patent 7,454,597 (Krishnan Kailas, Ravi Nair, Sumedh Sathaye, Wolfram Sauer, J-D Wellman).

Selected Recent Talks/Panels:

  • Invited Luminary talk, "Challenges of Computing System Design in the Generative AI Era", 37th International Conference on VLSI Design, Kolkata, India, January 2024.
  • Keynote presentation, “Evolution of Computing Systems and Sustainability in the Generative AI era”, Annual TxACE Symposium, University of Texas, Dallas, TX, October 2023.
  • Invited Panel, “AI vs. AC: Will Artificial Intelligence’s Expanding Energy Appetite Leave Enough to Keep Our Air Conditioners Running?”, Annual TxACE Symposium, University of Texas, Dallas, TX, October 2023.
  • Invited talk, “AI Hardware Innovations at IBM Research”, SRC AI Hardware Research Program Annual review, September 2021.