Alper Buyuktosunoglu

Overview

Title

Principal Research Scientist

Location

IBM Research - Yorktown Heights Yorktown Heights, NY USA

Bio

Alper Buyuktosunoglu received PhD degree in electrical and computer engineering from University of Rochester. Currently, he is a Principal Research Scientist in Efficient and Resilient Systems department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM z Systems and IBM POWER Systems in the areas of computer architecture and robust power management. He has over 200 patents, has received several IBM-internal awards, has published over 140 papers, and has served on various conference technical program committees in these areas. He also has served on the editorial board of IEEE MICRO. Dr. Buyuktosunoglu is a member of the IBM Academy of Technology, Hall-of-fame of MICRO, Hall-of-fame of HPCA, an IBM Master Inventor and an IEEE Fellow.

Publications

SoCurity: A Design Approach for Enhancing SoC Security
- - Naorin Hossain
  - Alper Buyuktosunoglu
  - et al.
- 2023
- DAC 2023
SoCurity: A Design Approach for Enhancing SoC Security
- - Naorin Hossain
  - Alper Buyuktosunoglu
  - et al.
- 2023
- IEEE Computer Architecture Letters
Characterization and exploration of latch checkers for efficient RAS protection
- - Karthik Swaminathan
  - Ramon Bertran
  - et al.
- 2023
- DSN 2023
7th Workshop on Cognitive Architectures (CogArch 2023)
- - Roberto Gioiosa
  - David Trilla Rodriguez
  - et al.
- 2023
- ISCA 2023
TokenSmart: Distributed, Scalable Power Management in the Many-core Era
- - Parth Shah
  - Ranjal Gautham Shenoy
  - et al.
- 2022
- ACM TACO
Prune, Permute and Expand: Efficient Machine Learning under Non-Client-Aided Homomorphic Encryption
- - Ehud Aharoni
  - Moran Baruch
  - et al.
- 2022
- MICRO 2022
On the Scalability of HeapCheck
- - Rick Boivie
  - Gururaj Saileshwar
  - et al.
- 2022
- DSN-S 2022
AI Accelerator on IBM Telum Processor Industrial Product*
- - Cedric Lichtenau
  - Alper Buyuktosunoglu
  - et al.
- 2022
- ISCA 2022
HeapCheck: Low-cost Hardware Support for Memory Safety
- - Gururaj Saileshwar
  - Rick Boivie
  - et al.
- 2022
- ACM TACO
IBM Telum: a 16-Core 5+ GHz DCM
- - Ofer Geva
  - Chris Berry
  - et al.
- 2022
- ISSCC 2022

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Patents

- 13 Apr 2010
- US
- 7698249
System And Method For Predicting A Hardware And/or Software Metrics In A Computer System Using Models
- 01 Dec 2009
- US
- 7627742
Method And Apparatus For Conserving Power By Throttling Instruction Fetching When A Processor Encounters Low Confidence Branches In An Information Handling System
- 03 Feb 2009
- US
- 7487012
Methods For Thermal Management Of Three-dimensional Integrated Circuits
- 18 Nov 2008
- US
- 7454573
Cost-conscious Pre-emptive Cache Line Displacement And Relocation Mechanisms
- 05 Nov 2008
- CN
- ZL200610005935.4
Arrangements For Reducing Latency And Snooping Cost In Non-uniform Cache Memory Architectures
- 04 Nov 2008
- US
- 7447923
Systems And Methods For Mutually Exclusive Activation Of Microprocessor Resources To Control Maximum Power
- 01 Sep 2008
- US
- 7421601
Method And System For Controlling Power In A Chip Through A Power-performance Monitor And Control Unit
- 24 Jun 2008
- US
- 7392366
Adaptive Fetch Gating In Multithreaded Processors, Fetch Control And Method Of Controlling Fetches
- 30 Jan 2007
- US
- 7170772
Apparatus And Method For Dynamic Control Of Double Gate Devices
- 20 Sep 2005
- US
- 6946869
Method And Structure For Short Range Leakage Control In Pipelined Circuits

Top collaborators

Alper Buyuktosunoglu

Overview

Title

Location

Bio

Publications

SoCurity: A Design Approach for Enhancing SoC Security

SoCurity: A Design Approach for Enhancing SoC Security

Characterization and exploration of latch checkers for efficient RAS protection

7th Workshop on Cognitive Architectures (CogArch 2023)

TokenSmart: Distributed, Scalable Power Management in the Many-core Era

Prune, Permute and Expand: Efficient Machine Learning under Non-Client-Aided Homomorphic Encryption

On the Scalability of HeapCheck

AI Accelerator on IBM Telum Processor Industrial Product*

HeapCheck: Low-cost Hardware Support for Memory Safety

IBM Telum: a 16-Core 5+ GHz DCM

Patents

System And Method For Predicting A Hardware And/or Software Metrics In A Computer System Using Models

Method And Apparatus For Conserving Power By Throttling Instruction Fetching When A Processor Encounters Low Confidence Branches In An Information Handling System

Methods For Thermal Management Of Three-dimensional Integrated Circuits

Cost-conscious Pre-emptive Cache Line Displacement And Relocation Mechanisms

Arrangements For Reducing Latency And Snooping Cost In Non-uniform Cache Memory Architectures

Systems And Methods For Mutually Exclusive Activation Of Microprocessor Resources To Control Maximum Power

Method And System For Controlling Power In A Chip Through A Power-performance Monitor And Control Unit

Adaptive Fetch Gating In Multithreaded Processors, Fetch Control And Method Of Controlling Fetches

Apparatus And Method For Dynamic Control Of Double Gate Devices

Method And Structure For Short Range Leakage Control In Pipelined Circuits

Top collaborators

Karthik Swaminathan

Aporva Amarnath

Subhankar Pal

Augusto Vega