Publications

58 results for Terence B. Hook

Impact of back bias on ultra-thin body and BOX (UTBB) devices
- - Q. Liu
  - Frederic Monsieur
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Ultra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology
- - Q. Liu
  - A. Yagishita
  - et al.
- 2011
- CSTIC 2011
Transistor mismatch properties in deep-submicrometer CMOS technologies
- - Xiaobin Yuan
  - Takashi Shimizu
  - et al.
- 2011
- IEEE T-ED
Reduction of RTA-driven intra-die variation via model-based layout optimization
- - J.C. Scott
  - O. Gluschenkov
  - et al.
- 2009
- VLSI Technology 2009
SOI antennas and wafer bulk connection
- - Terence B. Hook
  - Mario M. Pelella
- 2008
- IEEE International SOI Conference 2008
Gate-induced-drain-leakage current in 45-nm CMOS technology
- - Xiaohin Yuan
  - Jae-Eun Park
  - et al.
- 2008
- IEEE T-DMR
Analysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond
- - Jeffrey B. Johnson
  - Terence B. Hook
  - et al.
- 2008
- IEEE Electron Device Letters
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
- - Xiaobin Yuan
  - Jae-Eun Park
  - et al.
- 2007
- IIRW 2007
Technology elements of a common platform bulk foundry offering (invited)
- - P. Gilbert
  - A. Steegen
  - et al.
- 2007
- IEDM 2007