About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IIRW 2007
Conference paper
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
Abstract
Gate-induced-drain-leakage (GIDL) current in 45 nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2 V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling of electrons through the reverse-biased channel-to-drain p-n junction. A band-to-band tunneling model is used to fit the measured GIDL currents under different channel-doping levels and bias conditions. Good agreement is obtained between the modeled results and experimental data. ©2007 IEEE.