Transistor sizing of custom high-performance digital circuits with parametric yield considerations
- Daniel K. Beece
- Jinjun Xiong
- et al.
- 2010
- DAC 2010
Publications
Date
Featured collections
Popular topics
13 results for Daniel K. Beece
Cellular supercomputing with system-on-a-chip
- G. Almasi
- G. Almasi
- et al.
- 2002
- ISSCC 2002
SLS - A fast switch level simulator for verification and fault coverage analysis
- Z. Barzilai
- D. Beece
- et al.
- 1986
- DAC 1986
An overview of the Bluegene/L supercomputer
- N.R. Adiga
- G. Almasi
- et al.
- 2002
- ACM/IEEE SC 2002
Design methodology for the high-performance G4 S/390 microprocessor
- K.L. Shepard
- S. Carey
- et al.
- 1997
- ICCD 1997
The Eve companion simulator
- D. Beece
- R. Damiano
- et al.
- 1990
- EDAC 1990
SWITCH-LEVEL SIMULATION FOR MEMORY MAPPED GENERAL PURPOSE PARALLEL PROCESSORS.
- D. Beece
- J. Goren
- et al.
- 1985
- ICCD 1985
Transistor sizing of custom high-performance digital circuits with parametric yield considerations
- Daniel K. Beece
- Chandu Visweswariah
- et al.
- 2013
- Optimization and Engineering
First-order incremental block-based statistical timing analysis
- Chandu Visweswariah
- Kaushik Ravindran
- et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification strategy for the Blue Gene/L chip
- Michael E. Wazlowski
- Narasimha R. Adiga
- et al.
- 2005
- IBM J. Res. Dev