Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drainK. ChengA. Khakifiroozet al.2009VLSI Technology 2009
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitancesElbert HuangEric Josephet al.2008IEEE International SOI Conference 2008
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processingM. ChudzikB. Doriset al.2007VLSI Technology 2007
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS EraHemanth JagannathanSusan Fanet al.2023SSDM 2023
Physical characterization of sub-32-nm semiconductor materials and processes using advanced ion beam-based analytical techniquesM. HopstakenD. Pfeifferet al.2012Surface and Interface Analysis