NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Publications
22 results for Susan Su Chen Fan
First Demonstration of 16nm Pitch Subtractive Ru Interconnects for Advanced Technology Nodes
- C. Penny
- K. Motoyama
- et al.
- 2025
- IITC 2025
Development of Epitaxial SiGeB as a Test Vehicle to Evaluate Source-Drain Etchout during Channel Release of Gate-all-Around Devices: Topic/category: AEPM: Advanced Equipment Processes and Materials
- M. Nasseri
- C. Durfee
- et al.
- 2024
- ASMC 2024
Next Generation Infrared (IR) Laser Debonding / Silicon Handle Technology for Precision Chiplet Technology Applications
- Qianwen Chen
- Michael Belyansky
- et al.
- 2023
- ECTC 2023
Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Middle of line RC performance study at the 7 nm node
- Susan Su Chen Fan
- James H.-C. Chen
- et al.
- 2017
- IITC 2017