Middle of line RC performance study at the 7 nm node

Abstract

In this paper, a study on MOL (middle-of-the-line) RC performance and optimization of MOL resistance at both source/drain contact and local interconnect level at 7 nm node is presented. We focus on the device delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on a real 10 nm FINFET device. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, using this model the impact of the MOL on the circuit performance can be determined. By using a liner-free W (tungsten) metallization at source drain contact level and Co (cobalt) or Ru (ruthenium) metallization in the MOL local interconnect level, a 45% reduction in MOL resistance was obtained which is crucial to achieve a better 7 nm MOL performance over the 10 nm node.