Middle of Line (MOL) metallization with cobalt has been very promising to reduce the parasitic resistance of advanced CMOS devices. Though significant line resistance reduction has been demonstrated, there are still many challenges in cobalt MOL integration especially for yield improvement. In this study, via resistance and yield are found to be related to the queue time from cobalt CMP to dielectric cap deposition. The failure analysis shows cobalt erosion causing open via resistance. Cobalt erosion is caused by moisture and residual fluorine gas in the FOUP. By using N2 purged FOUP, the via resistance yield is improved.