A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
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15 results for W. Reohr
Rethinking refresh: Increasing availability and reducing power in dram for cache applications
- Philip G. Emma
- William R. Reohr
- et al.
- 2008
- IEEE Micro
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A High-Speed 128-kb MRAM Core for Future Universal Memory Applications
- John DeBrosse
- Dietmar Gogl
- et al.
- 2004
- IEEE Journal of Solid-State Circuits
Memories of tomorrow
- William Reohr
- Heinz Hönigschmid
- et al.
- 2002
- IEEE Circuits and Devices Magazine