Ratioed CMOS: A low power high speed design choice in SOI technologies

Abstract

Ratioed CMOS gates implemented in a partially-depleted (PD) SOI CMOS technology are usually considered to be high power but will end up being both faster and lower power than other circuit implementations mainly due to the reduced junction capacitance in SOI devices as well as floating-body effects. As an example, a high performance multiplier shifter is 3 to 4 times faster and dissipates 9 times less power than more conventional implementations.