Ultrathin high-K gate stacks for advanced CMOS devices

In this paper we review recent progress in and outline the issues for high-K high-temperature (∼1000°C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO2, Al2O3, HfO2/Al2O3, ZrO2, silicates, and AlNy(Ox) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.