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Publication
Technical Digest-International Electron Devices Meeting
Paper
Triple-self-aligned, planar double-gate MOSFETs: Devices and circuits
Abstract
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/ebeam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.