Using silicon for microcooler fabrication is advantageous over metals as it can be micromachined for smaller fin wall and channel width dimensions, increasing the thermal heat transfer coefficient [1,2]. Since the fin height is limited by the wafer thickness, multiple microcoolers are stacked to increase the total fin height to enhance the heat transfer from a chip. Stacked silicon microcoolers have been previously designed, fabricated, and characterized for thermal performance . Figure 1 shows the schematic drawing and the photograph of a stacked silicon microcooler. The thermal performances of both package-integrated (Figure 2) and separable stacked silicon microcoolers were tested for same chip dimensions, dissipated power, and water flow rate. A comparison of the thermal performances of both the cases showed that the package integrated microcooler has significantly smaller thermal resistance to heat transfer, as shown in Figure 3. A performance of 20 mm2C/W was measured for the integrated microcooler with spatially uniform chip power dissipation. In a multi-core processor package, the power density across the chip surface is highly nonuniform; the power density in the cores can be 4-6 times that outside the cores. In this study, we explore a variety of non-uniform power distributions on the chip surface for characterizing the thermal performance of integrated stacked silicon microcoolers. An array of individually controllable heaters, present on the test chip, is used to generate heating patterns corresponding to high-power computing cores. The thermal resistance to the heat transfer across the microcooler and the pressure drop in the water flow across the microcooler are characterized as a function of the flow rate. The cooling power limits of such high-power computing core maps are also defined. Finally, a numerical analysis is performed for the non-uniform power dissipation cases to validate the experimental results.