A Multiscale Workflow for Thermal Analysis of 3DI Chip Stacks

Thermally aware design of 2.5D and 3D advanced packaging systems will require fast, accurate, and powerful thermal analysis of chiplets, stacks, and packages. These systems contain multiple materials, non-linear heat transfer, and geometric feature sizes that span twelve orders of magnitude. Simulations that can resolve smallest heterostructures in the Front-End-Of-Line transistors and Back-End-Of-Line interconnects present significant thermal modeling and analysis challenges in isolation. Together, as part of a full chip stack, full resolution models cannot meet the speed and accuracy needs of the design process. Further, establishing precise parameter values for the materials in these systems, when size and temperature dependencies create significant deviations from bulk properties is a challenge. To address these issues, we have developed a multiscale methodology that advances the current state of the field by enabling package scale simulations that include microstructural details at the size of the BEOL interconnects and integrates with industry standard design files. Taking advantage of the large-scale separation between the BEOL interconnects and the package level structures, we employ a hierarchical multiscale finite element scheme. The hierarchical scheme uses a standard finite element formulation on the packages scale and uses computational homogenization to obtain effective thermal conductivities in the BEOL. This requires solving a secondary finite element problem at every package-level integration point that has a representative geometric structure of the surrounding material, typically called a representative volume element (RVE).

In our multiscale workflow, geometric models of these RVEs are automatically constructed, meshed, and used to compute homogenized thermal conductivities on-the-fly from GDS2/OASIS based on the finite element integration point locations. Here, we make use of a direct, static-condensation based method to extract the full thermal conductivity tensor.

This scheme requires size-dependent thermal conductivities of the dielectrics and metals that make up the RVEs, that contain geometric features on the size of BEOL interconnects. To that end, we use the 3w technique to characterize the anisotropic thermal conductivities of thin-film dielectrics. We also propose a model validation methodology that uses a 3w heater along with an array of temperature probes to validate our models on simple test structures.

At the time this abstract is submitted, the team has implemented a workflow that ingests GDS2/OASIS files and automatically constructs and meshes RVEs. We have additionally, implemented the homogenization scheme on an ad-hoc basis. Automatic extraction of the homogenized properties is ongoing. Our team has additionally measured a through-thickness and cross-plane conductivities for a range of film thicknesses in dielectrics using 3w sensors. Construction of validation structures is ongoing.