With increasing processing capability and power consumption in multi-layered micro-electronic packages, efficient thermal management and structural integrity continue to remain crucial factors for ensuring package reliability. Effective and simple to implement analytical methods for temperature and warpage prediction are important tools to predict the thermo-mechanical performance of a package. While many existing analytical thermal models predict exact or approximate solutions , , they are computationally expensive for non-uniform power distributions and do not account for the effect of thermal warpage on the package thermal resistances and the temperature distribution. Similarly, existing methodologies for calculating the warpage or thermal stresses in bi- and multi-layer strip ,  do not consider non-uniform power distribution on the chip surface.This paper presents an analytical solution for the temperature distribution in a multilayer chip-on-spreader package, combining the thermal warpage of the chip and package with the imposed uniform and non-uniform power distributions on the chip. An analytical solution is developed to calculate the warpage and the radius of curvature for a multilayer unlidded package as a result of mismatch in the thermal expansion of the package components as its temperature varies. The model is verified against Timoshenko's model for two layers and is found to be a match. The temperature distribution on the chip is calculated using an analytical method for an unwarped package  where the linear superposition principle is applied to an exact solution of heat transfer in the spreader, coupled with 1D heat conduction from the chip and the thermal interface material (TIM) to the spreader. The two methods are solved implicitly until a converged solution is reached. The temperature distribution and the warpage results are presented for 10 by 10 grid uniform and non-uniform power maps applied to the chip. The model predicts a significant change in the temperature distribution as a result of package warpage. The results are also reported for a 60 by 60 grid non-uniform power map representative of power dissipation in a server chip. A comparison between the analytical model and the numerical results is also presented and are found to be in good agreement.