High-k/Metal Gates are ubiquitous in CMOS chips and are a product of intense collaborative research across academia and corporate labs. These new materials re-enabled a roadmap for CMOS scaling from FinFET (current) to Nanosheet (future) device architectures. However, CMOS scaling is slowing down with performance benefits diminishing with each node. At the same time, the need for consuming data has gone up exponentially with deep learning-based AI algorithms being deployed for this purpose and run on specialized AI hardware such as graphical processing units (GPU). However, GPUs consume significant power since data transfer occurs from memory to processor. Resistive Processing Units (RPU) envision artificial neural networks mapped to arrays of non-volatile memory (NVM) elements that execute operations in-memory and constant time, thereby enabling significant power performance benefits. Many NVM elements are being evaluated as RPU but suffer from significant non-idealities and are therefore ripe once again for innovation and collaboration across academia and industry.