IEDM 2018
Conference paper

High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy

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We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of ∼10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm-L g device shows a peak g m of 1.37 mSμm, a subthreshold slope in saturation of 72 mV/decade, and an I on of 355 μ Aμm at 0.5 V V gs, the highest among reported sub-50 nm-L g III-V FETs on Si.