Strain mapping of Si devices with stress memorization processing

Abstract

Dual lens dark field electron holography and Moiré fringe mapping from dark field scanning transmission electron microscopy are used to map strain distributions at high spatial resolution in Si devices processed with stress memorization techniques (SMT). It provides experimental evidence that strain in the Si channel is generated by dislocations resulting from SMT. The highest value of strain, up to 1.1% (1.9 GPa in stress) occurs at the Si surface along the channel direction: 110. An increase of ∼0.2% strain in the channel is observed after removing the poly-Si gate through the replacement high-k metal gate process. © 2013 AIP Publishing LLC.