In this paper, a strategy of performing segment removal in an SAQP (self-aligned quadruple patterning) and its implication on interconnect parasitic capacitance are reported. In order to reduce the cost and process complexity, through process emulations, this study specifically focuses on not introducing additional lithography step(s) or material to the conventional SADP (self-aligned double patterning) integration. Four SAQP process integrations are demonstrated to selectively remove dummy lines in between the signal lines from sea of lines, as a result, the line to line capacitance can be reduced. The conventional non-mandrel block lithography step will only remove every other line. Typically, to remove more lines requires an additional hard mask layer and a first non-mandrel block lithography step where the line to line capacitance can be further reduced. However, in this study, a double spacer transfer scheme is proposed to achieve the same final structure but without the additional hard mask layer and lithography step. Therefore, this could be another option for 7 nm or 5 nm process integration of BEOL interconnects.