IEEE Journal of Solid-State Circuits

Resonant clocking using distributed parasitic capacitance

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A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-μm partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.