'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
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51 results for Kevin Nowka
A 1V 18GHz clock generator in a 65nm PD-SOI technology
- Fadi H. Gebara
- Jeremy D. Schaub
- et al.
- 2007
- ISSCC 2007
Requirement-based design methods for adaptive communications links
- Juan Antonio Carballo
- Kevin Nowka
- et al.
- 2004
- DAC 2004
A 0.9 V to 1.95 V dynamic voltage-scalable and frequency-scalable 32 b powerPC processor
- Kevin Nowka
- Gary Carpenter
- et al.
- 2002
- ISSCC 2002
A 0.9 V to 1.95 V dynamic voltage-scalable and frequency-scalable 32 b PowerPC processor
- Kevin Nowka
- Gary Carpenter
- et al.
- 2002
- ISSCC 2002
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
Circuit design for low power
- Kevin Nowka
- 2005
- HCS 2005
A 32nm 0.5V-supply dual-read 6T SRAM
- Jente B. Kuang
- J. Schaub
- et al.
- 2010
- CICC 2010
Statistical yield analysis of silicon-on-insulator embedded DRAM
- R. Kanj
- R.V. Joshi
- et al.
- 2009
- ISQED 2009
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- J.B. Kuang
- A. Mathews
- et al.
- 2008
- ESSCIRC 2008