Publication
ECS Meeting 2015 Chicago
Conference paper

Record-performance In(Ga)As MOSFETs targeting ITRS high-performance and low-power logic

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Abstract

We review development of In(Ga)As-channel MOSFETs. InAs and InGaAs channels, combined with thin gate dielectrics, provide high transconductance, but off-state leakage can be high due to bandband tunneling currents. This leakage is reduced through thin 2.5-3nm channels, and through InGaAs or InP vertical field spacers in the raised source and drain. Devices with 2.7nm InAs channels and lightly-doped InGaAs source/drain spacers, at 25nm L<inf>g</inf>, provide a record 0.5mA/μm I<inf>on</inf> at 100nA/μm I<inf>off</inf> and 500mV V<inf>DD</inf>. 1 μm L<inf>g</inf> FETs show 61mV/decade subthreshold swing at V<inf>DD</inf>=0.1 V. Targeting the LP specification, we have developed InGaAschannel MOSFETs with lightly-doped InP wide-bandgap source/drain spacer layers. At 30nm gate length, these show a minimum 60 pA/μm I<inf>off</inf>, approximately 100:1 smaller than a similar device using InGaAs source/drain spacers. A FET using InP spacers, with 45 nm gate length, shows 0.15 mA/μm I<inf>on</inf> at 1nA/μm I<inf>off</inf> and 500mV V<inf>DD</inf>.

Date

24 May 2015

Publication

ECS Meeting 2015 Chicago

Authors

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