Strained Silicon-Germanium (s-Si<inf>1-x</inf>Ge<inf>x</inf>) FinFET is a promising pMOS candidate for sub-10nm technology generations due to its superior hole transport properties over Si FinFETs, which is a result of built-in uniaxial compression. In this paper, we discuss process integration challenges and opportunities as well as electrical characterization of s-Si<inf>1-x</inf>Ge<inf>x</inf>-on-Insulator (SiGeOI or SGOI) FinFETs with aggressively scaled gate and fin dimensions and Ge content up to x∼0.5, using an improved Si-cap-free surface passivation process. The device electrostatics, hole transport, impact of surface passivation, and drain leakage characteristics of SiGeOI pMOS FinFETs are comprehensively studied. The results indicate that SiGeOI FinFETs with moderate Ge content of x∼0.3 can offer superior pMOS characteristics and are promising candidate for high-performance (HP) and some low-power applications (LP). On the other hand, while SiGeOI FinFETs with higher Ge content (x∼0.5) can offer extremely high mobility and high current drive which is applicable to high-performance CMOS, their off-state leakage could be a concern for low-power applications.