IEEE International SOI Conference 2009
Conference paper

Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator

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Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling. © 2009 IEEE.