A high-density SRAM design technique using silicon nanowire FETs
- Yi-Bo Liao
- Meng-Hsueh Chiang
- et al.
- 2011
- LISS 2011
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16 results for Meng-Hsueh Chiang
Variability study of silicon nanowire FETs
- Yi-Bo Liao
- Meng-Hsueh Chiang
- et al.
- 2011
- NSTI-Nanotech 2011
High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application
- Chun-Yu Chen
- Jyi-Tsong Lin
- et al.
- 2010
- IEEE International SOI Conference 2010
Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator
- Chun-Yu Chen
- Yi-Bo Liao
- et al.
- 2009
- IEEE International SOI Conference 2009
Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM
- Ashish Goel
- Sumeet Gupta
- et al.
- 2009
- DRC 2009
Asymmetrical triple-gate FET
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2007
- SISPAD 2007
Discrete dopant fluctuation in limited-width FinFETs for VLSI circuit application: A theoretical study
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2006
- ICICDT 2006
Optimal design of nanoscale triple-gate devices
- Meng-Hsueh Chiang
- Tze-Neng Lin
- et al.
- 2006
- IEEE SOI 2006
High-density logic techniques with reduced-stack double-gate MOSFETs
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- IEEE International SOI Conference 2005
Single polysilicon gate high-density logic using independently-controlled double-gate devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- A-SSCC 2005