OPTIMAL CODE GENERATION ALGORITHMS FOR ARITHMETIC EXPRESSIONS EXECUTING ON PIPELINED, DECOUPLED ARCHITECTURES.

Abstract

The problem of efficient generation of code to evaluate arithmetic expressions under varied assumptions of the underlying execution model is considered. A RISC-style load/store instruction set architecture is assumed throughout. Initially, a simple, nonpipelined, strictly serial execution model with N registers is considered. The machine model is then modified to allow pipelined execution of a single instruction stream. Finally, a decoupled access/execute model is considered in which each (decoupled) unit is pipelined.