CONSIDERING TIMING CONSTRAINTS IN SYNTHESIS FROM A BEHAVIOURAL DESCRIPTION.

Abstract

An approach is presented to include timing information in behavioral level specifications, check its consistency, and use it in the automatic synthesis of circuit structures. Timing is specified in DSL (digital system specification language) by imposing constraints on single operations or on groups of operations. This information is represented by attributed graphs. An algorithm to check consistency using these graphs is described. Synthesis requires this timing information during module allocation and also when eventually rearranging operations to increase parallelism or to achieve a better hardware allocation.