CLOCK GENERATOR WITH FINITE STATE MACHINE OPTIMIZATION.

Abstract

The logic and circuit design of an on-chip four-phase clock generator for the Micro-270 32-bit microprocessor, implemented as a finite-state machine, is described. The design combines the adjacent states of a state diagram, constructed using conventional techniques, to form a new state diagram. This reduces the number of states, logic and wiring complexity, and power and area consumption. The design also utilizes a pipelined and preconditioned organization to provide high-performance and spike-free clock pulses. It is very flexible, easily accommodating changes in the number of clock signals, clock loading and timing.