OpenCAPI memory interface signal integrity study for high-speed DDR5 differential DIMM channel with standard loss FR-4 material and SNIA SFF-TA-1002 connector
DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and will be introduced to the market in 2020. DDR5 DDIMM uses OMI (OpenCAPI Memory Interface) as the host interface. On the DDIMM printed circuit board (PCB), the minimum data transfer rate per data differential pair over the OMI bus is 25.6Gbps. This is a significant data rate increase for DRAM modules over conventional single-ended data transferring DIMMs. For example, the DDR5 LRDIMM data transfer rate per pin is 3.2Gbps. Careful attention must be paid to the bill of materials of the DDIMM to control its cost towards general market acceptance of this new DIMM technology. As a result, it is desired to use standard loss FR-4 material to build the DDIMM PCB. Validating the DDIMM PCB wiring for the high-speed differential memory bus requires accurate high-speed link simulations. These simulations require accurate models representing differential wiring in the DDIMM PCB stack-up. The models must be built using not only representative physical dimensions but also accurate frequency dependent material properties obtained through PCB characterization. The Short Pulse Propagation (SPP) method will be used to extract PCB frequency dependent material properties. PCB suppliers usually have different Copper Clad Laminate (CCL) and prepreg material set selections largely due to the supplier relations. The test coupons of this study will be built using CCL and prepreg materials from two suppliers. System level differential memory bus simulation based on SPP characterization will be performed and the simulation results from different material/stack-up designs will be benchmarked. DDR5 DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector which differs significantly from the JEDEC RDIMM connector for improved electrical signaling characteristics. In this work, the SNIA high-speed connector to PCB interface design will be studied as it is of utmost importance for achieving good signal integrity. In addition to high speed signal integrity, the DDIMM PCB mechanical interaction with the SFF-TA-1002 connector is studied and it will be highlighted in this paper. The PCB mechanical outline design proposal is made to mitigate module/connector mechanical interference. To understand the PCB yield impact, DIMM PCB suppliers' process capabilities for critical feature/dimensions will be studied as well.