This work presents the modeling and the multi-objective optimization of a 2.5D inductor-based Fully Integrated Voltage Regulator (FIVR) with respect to efficiency η and/or chip area power density α, i.e. based on the η-α-Pareto-front, for microprocessor applications. The Voltage Regulator consists of a four-phase interleaved buck converter operated in Continuous Conduction Mode (CCM). The rated power of the considered converter is 1W, and input and output voltages are constant and equal to Vin = 1.7V and Vout = 0.85V. The optimization employs analytical models for the switches, which reside on chip and are manufactured in a 32nm CMOS SOI process, and for the passive components, i.e. racetrack inductors with magnetic core material and deep-trench capacitors that are fabricated in a silicon interposer. The optimization procedure considers thermal aspects and disregards solutions that lead to excessive component temperatures. According to the optimization results, either high efficiencies, greater than 90%, or high area power densities, with chip power densities greater than 20W/mm2 and interposer power densities higher than 1.5W/mm2 are achievable. The optimized design point, selected from the η-α-Pareto-front, features an efficiency of 90.1%, interposer power density of 0.309W/mm2, and a chip power density of 27.4W/mm2.