Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs

Abstract

We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kane's tunneling model for direct bandgap (Eg) materials and compare it with experimental results. Moreover, studying the activation energy (EA) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.