A dual-side cooling topology is proposed that is achieved by embedding a power insert into the organic substrate of a chip or chip stack. The power insert consists of vertical copper lamellas supporting lateral current feed in addition to vertical heat dissipation at minimal electrical and thermal gradients. The lateral current feed capability is key to enable the introduction of the cold plate on the bottom side of the substrate. Thermal and electrical finite-element modeling was performed to determine the optimal pitch of the power insert lamella of 270 μm and 350 μm to obtain a total thermal resistance of 21 K-mm2/W and a voltage drop of 2 mV, respectively. The 10 × 10 mm2 power inserts are fabrication by means of a copper and prepreg lamination process, followed by a sawing and polishing singulation step. The embedding of the power insert is described, considering additional redistribution layers to accommodate also smaller interconnect pitches on the chip side. The effective thermal conductivity of the power insert was derived by bulk-thermal measurement and yielded 320±50 W/m-K, ten times the performance of state-of-the-art substrates with thermal via arrays. Finally, we demonstrate the benefits of the dual-side cooling approach in a thermal benchmark study that compares it with back- and front-side cooling. Dual-side cooling not only halfs the total thermal resistance, but also enables the integration of pyramid-like chip stacks and the placement of high-power dies in the bottom tiers of a stack.