IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

ELIAD: Efficient Lithography Aware Detailed routing algorithm with compact and macro post-OPC printability prediction

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In this paper, we present an efficient lithography aware detailed (ELIAD) router to enhance silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first quantitatively show that a pre-OPC litho-metric is highly uncorrelated with a post-OPC metric, which stresses the importance of a post-OPC litho-metric for design-time optimization. We then propose a compact post-OPC litho-metric for a detailed router (DR) based on statistical characterization, where the interferences among predefined litho-prone shapes are captured as a lookup table. Our litho-metric derived from the characterization shows high fidelity to the total edge placement error (EPE) in large scale, compared with Calibre OPC/optical rule check. Therefore, ELIAD powered by the proposed litho-metric can enhance the overall post-OPC printed silicon image. Experimental results on 65-nm industrial circuits show that ELIAD outperforms a rip-up/rerouting approach such as Resolution- enhancement-technique-Aware Detailed Routing with 8 × more EPE hot spot reduction and 12 × speedup. Moreover, compared with a conventional DR, ELIAD is only about 50% slower. © 2006 IEEE.