Layout optimizations for double patterning lithography

Abstract

Deep sub-wavelength lithography is one of the most fundamental challenges for future scaling beyond 32nm as the industry is currently stuck at the 193nm lithography. Many ingenious technologies/tricks are developed to push the limit of 193nm lithography, e.g., immersion lithography and computational lithography. But they may not be sufficient for 22nm patterning. Meanwhile, nextgeneration lithography, such as EUV (Extreme Ultra-Violet) lithography may not be available for mass production in the near future. As a practical solution, double patterning lithography (DPL) has become a leading candidate for 22nm (and likely 16nm) lithography process. DPL poses new challenges for overlay control, layout decomposition, and up-stream physical designs. In this paper, we will discuss some recent advancements and challenges in layout decompositions and DPL friendly layout optimizations. ©2009 IEEE.