Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
As the technology scales, process variations and model inaccuracies impact design yield. In this paper, we demonstrate a statistical analysis methodology targeting both memory and custom logic design applications. For advanced technologies, we extend the methodology to enable key features such as FEOL and BEOL parasitic extraction and TCAD for manufacturability. This increases the statistical confidence in the functionality and operability of the system-on-chip as a whole. We present design case studies both in planar and non-planar technologies.
Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
Dinesh Kushwaha, Ashish Joshi, et al.
ISQED 2024
Leibin Ni, Zichuan Liu, et al.
IEEE JXCDC
Rajiv V. Joshi, Keunwoo Kim, et al.
IEEE Transactions on VLSI Systems