Designing stable circuits in the world of instability

Abstract

As the technology scales, process variations and model inaccuracies impact design yield. In this paper, we demonstrate a statistical analysis methodology targeting both memory and custom logic design applications. For advanced technologies, we extend the methodology to enable key features such as FEOL and BEOL parasitic extraction and TCAD for manufacturability. This increases the statistical confidence in the functionality and operability of the system-on-chip as a whole. We present design case studies both in planar and non-planar technologies.