Publication
ISSCC 2021
Conference paper

24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology

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Abstract

8T SRAM, using domino read, is preferred for small-size and high-performance arrays [1]. Ripple domino circuitry relies on rail-to-rail readout, which forces a trade off between performance and the number of 8T cells on a local read bit line (RBL). To support larger array sizes, without sacrificing performance, arrays are segmented, and several segments are stitched to form the full array. Each segment requires local evaluation circuitry to connect local BL to global BLs. This local circuitry, along with the required layout fencing of each segment results in poor array efficiency.

Date

13 Feb 2021

Publication

ISSCC 2021

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