IEDM 2008
Conference paper

Demonstration of highly scaled FinFET SRAM cells with high-Κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

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Highly scaled FinFET SRAM cells, of area down to 0.128μm2, were fabricated using high- κdielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vtvariation of Fin- FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187μm2 cell, at V d = 0.6 V a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. σVt of transistors in 0.187μm2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a pla- nar-FET SRAM cell, which would have higher σVt mainly caused by heavy doping into the channel region.