Demonstration of highly scaled FinFET SRAM cells with high-Κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
- H. Kawasaki
- M. Khater
- et al.
- 2008
- IEDM 2008
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29 results for R. Viswanathan
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Very high performance 50 nm CMOS at low temperature
- S.J. Wind
- L.T. Shi
- et al.
- 1999
- IEDM 1999
Is selective CVD an improvement for the titanium silicide process in sub-quarter micron technology? A phase formation study using x-ray diffraction
- R.A. Roy
- Cryil Cabral Jr.
- et al.
- 1998
- MRS Spring Meeting 1998
Is selective CVD an improvement for the titanium silicide process in sub-quarter micron technology? A phase formation study using x-ray diffraction
- R.A. Roy
- Cryil Cabral Jr.
- et al.
- 1998
- MRS Spring Meeting 1998
In situ analysis of the formation of thin TiSi2 (<50 nm) contacts in submicron CMOS structures during rapid thermal annealing
- L. Clevenger
- C. Cabral Jr.
- et al.
- 1995
- MRS Fall Meeting 1995
Sub-30 nm abrupt P+ junction formation with Ge preamorphization and high energy Si co-implantation
- K.L. Lee
- Ted Zabel
- et al.
- 1999
- MRS Spring Meeting 1999
High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz fT
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1997
- IEEE Electron Device Letters
Looking into the crystal ball: Future device learning using hybrid E-beam and optical lithography
- S.E. Steen
- S.J. McNab
- et al.
- 2005
- Microlithography 2005
0.5 μm CMOS devices and circuits fabricated using synchrotron X-ray lithography
- L.K. Wang
- C.H. Hsu
- et al.
- 1989
- VLSI Technology 1989