Publication
IEEE T-ED
Paper

Demonstration of 3-D SRAM Cell by 3-D Monolithic Integration of InGaAs n-FinFETs on FDSOI CMOS with Interlayer Contacts

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Abstract

In this paper, we demonstrate, for the first time, 3-D Monolithic integration of short-channel replacement metal gate InGaAs n-FinFETs on fullydepleted silicon-on-insulator CMOS, with TiN/W interlayer contacts. Top layer InGaAs nFETs feature raised source-drain and bottom layer CMOS has Si raised source-drain for nFETs, SiGe raised source-drain for pFETS, implants, silicide, and TiN/W plug contacts. Scaled gate length (Lg) of 15 nm is achieved on bottom layer Si n- and pFETs, while the top layer InGaAs n-FinFETs are scaled to Lg of 25 nm. A densely integrated 3-D 6T-static random access memory circuit with planar InGaAs nFETs stacked on Si pFETs is demonstrated by taking advantage of the interlayer contacts. This yields significant area reduction when compared with 2-D layouts. Index Terms-3-D Monolithic (3-DM).

Date

01 Nov 2017

Publication

IEEE T-ED

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