A dense co-integration of nano-scaled InGaAs n-FETs and SiGe p-FETs is envisaged for future low power and high performance CMOS in sub-10 nm regime. It is, therefore, essential to have a scalable material and device integration scheme for such a hybrid CMOS. In this paper we detail an InGaAs integration method on large scale Si substrate using selective epitaxy in empty oxide cavities. We show how this method translates into a new concept for the realization of hybrid InGaAs/SiGe CMOS circuits. We then report n- and p-MOSFETs obtained by this integration scheme, as well as CMOS inverters and dense 6T-SRAM arrays.