About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ESSDERC 2017
Conference paper
Hybrid InGaAs/SiGe CMOS circuits with 2D and 3D monolithic integration
Abstract
Advanced CMOS nodes target high-performance at lower supply voltage. High-mobility III-V channel materials have the potential to meet this target. Although III-V materials such as InGaAs are beneficial for nFET channels, SiGe (or Ge) provides better hole mobility and is more suited for pFET channels. Therefore, a InGaAs/SiGe hybrid CMOS technology is being pursued for scaled nodes. There are significant challenges to cointegrate these two materials in a scalable process. In this regard, here, we present some of our recent work in InGaAs/SiGe CMOS integration through a novEl Direct epitaxy process for co-planar 2D integration. We also present our efforts in 3D monolithic integration of InGaAs-on-SiGe for CMOS and beyond.