Interconnects have become a severe bottleneck in today's computing hardware . For large-scale data centers in particular, the interconnect situation is even more severe . The interconnect bandwidth and bandwidth density have to be increased on all system-levels. The ideal technology to increase the density is Si photonics (SiPh). While the integration of most of the SiPh components has been mastered already on a 90 nm CMOS platform , the integration of III-V materials to yield directly-modulated lasers still poses a major challenge. This integration is considered as the cornerstone for reaching a complete, yet cost-competitive, SiPh-CMOS marriage. Most concepts shown so far [4, 5] either lack CMOS-compatibility or have device dimensions that hinder the integration of the laser into a standard BEOL. To allow for a common BEOL between SiPh and CMOS, we integrate the III-V material between the FEOL and BEOL, within the first interlayer dielectric ILD0' (Fig. 1). Such integration imposes tight requirements on device dimensions as well as several technological challenges that have to be mastered. We report here on decisive aspects of such integration. This represents a major step towards a full integration of III-V, SiPh and CMOS.