Investigations of silicon nano-crystal floating gate memories
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/I off characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4-5 GPa peak of lateral uniaxial tensile stress in the Si NW. © 2010 Elsevier Ltd.
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
R.M. Macfarlane, R.L. Cone
Physical Review B - CMMP
A. Nagarajan, S. Mukherjee, et al.
Journal of Applied Mechanics, Transactions ASME
T.N. Morgan
Semiconductor Science and Technology