A-SSCC 2013
Conference paper

A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology

View publication


This paper describes key design features of a 32-Gb/s 4-tap FFE/15-tap DFE transceiver in 32-nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low latency clock and data recovery (CDR) to improve high frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. The transceiver can equalize a channel with 30dB of loss at a bit-error rate below 10-12 while using 21 mW/Gbps at 1V supply and 0.7 mm2. © 2013 IEEE.