Publication
ISSCC 2016
Conference paper

A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

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Abstract

The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates up to 28Gb/s and 10-12dB insertion loss at Nyquist. Proprietary and open standards in the same speed range are being developed too for data and memory-centric systems co-designed with CPUs and GPUs and channels with insertion loss on the order of 20dB [2].

Date

23 Feb 2016

Publication

ISSCC 2016

Authors

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