As CMOS devices continue to scale down in voltage and area, digital-based high-speed serial I/Os  become increasingly competitive with analog-based designs [2,3]. In addition to offering the PVT-independent performance of digital functions and superior power and area scaling to future technology nodes, digital-based I/Os can support advanced line modulation techniques that will become necessary as long-reach electrical channel data rates scale to 56Gb/s and beyond. The key enablers of a digital receiver are power and area efficient analog to digital conversion (ADC) and digital channel equalization. This paper describes the design of a 25Gb/s 2-level digital serial line receiver including a -rate 5b flash ADC, an 8-tap feed-forward equalizer (FFE), an 8-tap decision-feedback equalizer (DFE), and a baud-rate clock and data recovery circuit (CDR). The receiver features a flash ADC, which employs a new power and area efficient slicer design capable of achieving high-precision (∼1mV) threshold accuracy with an associated on-chip calibration system. The 32nm SOI CMOS receiver achieves error-free operation with margin on a reflective transmission-line channel with 40dB half-baud loss.